Directory

Blog Directory
├── STM32F4 Peripheral Drivers
│   ├── CRC Calculation Unit (CRC)
│   ├── Direct Memory Access (DMA)
│   ├── Independent Watchdog Timer (IWDG)
│   └── Real-Time Clock (RTC)
├── STM32L4+ Peripheral Drivers
│   ├── Clock Tree for STM32L4Rxxx and STM32L4S5xxx
│   ├── AES Hardware Accelerator (AES)
│   ├── HASH Processor (HASH)
│   ├── Random Number Generator (RNG)
│   └── Digital Camera Interface (DCMI)
├── Projects
│   ├── Musical Keyboard using UART on Nucleo-F401
│   ├── SignGlove for Paralyzed Patients using an ESP32
│   ├── AESecureIO: Embedded Data Encryption and Storage Tool 
│   ├── CifradoPro: Baremetal Hardware Security Module on STM32L4
│   ├── Audio DSP Series
│   │   ├── Storing Audio Data on external Flash Memory
│   │   ├── Audio Echo processing on 16-bit PCM data
│   │   └── Audio Data Compression & Decompression using ADPCM
│   ├── Wear Leveling Subsystem for W25Q Flash Memories
│   └── Software Random Number Generator using Timers and Bitwise Operations
├── Buildroot
│   ├── Custom Image Generation for RPi4 using Buildroot
│   └── Cross-Compiling executables for RPi4 on x86_64
└── Hardware Tinkering
    └── Tearing Down the MicroHub/8 TP1008C 8-port Ethernet Repeater


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Cifradopro: A baremetal Hardware Security Module using the STM32L4S5 Cortex-M4 MCU

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Capturing images using the Digital Camera Interface | STM32L4 | DCMI | CMSIS

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Digital Camera Interface The DCMI (Digital Camera Interface) is a synchronous parallel interface designed to receive a high-speed data stream from an external CMOS camera module. It offers compatibility with 8-bit, 10-bit, 12-bit, or 14-bit camera modules.  The DCMI peripheral supports Embedded Line and Frame synchronization methods in addition to the Hardware Synchronisation from the CMOS Camera Module. It has two operating mode, namely Continuous or Snapshot mode. Additionally, it offers a crop feature and supports various data formats, including 8/10/12/14-bit progressive video (Monochrome or Raw Bayer), YCbCr 4:2:2 Progressive Video, RGB 565 Progressive Video, and Compressed Data in JPEG format.   For more information on the DCMI peripheral, read the Training material for DCMI on STM32L4 from STMicroelectronics . DCMI Registers The DCMI peripheral has Control and Status registers for the DCMI Core and Interrupts. It also has a few registers for handling Data synchronizatio...
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Designing a Software-Based Wear Leveling Subsystem for W25Q64FV Serial Flash Memory

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NOR Flash Memories & the Need for Wear Leveling NOR Flash is a type of non-volatile memory used to store data that needs to persist even when a device is powered off. NOR Flash is typically organized into sectors or blocks, which can be individually erased and reprogrammed.  Due to the physics of flash cell structure, memory cells suffer from “wear” with every Program/Erase cycle (P/E cycle). This means flash memory has a finite usable life. If a flash memory exceeds this limit, the storage capability becomes unreliable. Wear Leveling is a common technique used by storage media  to enhance the longevity of the storage media. Flash memory cells can only be programmed from a 1 to a 0 state. In order to set any cell from 0 to 1 state, the cell has to be erased to a 1. In order to update any already programmed memory sectors/blocks, the sectors/blocks have to be first erased and then reprogrammed, hence the P/E cycle. Depending on how of...
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