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Storing Audio data in an SPI Flash Memory This is the second article of the Audio Processing Project on the STM32 F411 Discovery Board. This article focuses on developing the SPI driver and the Library for the W25Q64FV 64 M-bit Serial Flash Memory from Winbond. The W25Qxx series of chips are Serial NOR Flash memory devices with capacities ranging from 4 MB to 128 MB and utilize the Serial Peripheral Interface for communication with microcontrollers. Checkout the STM32F411 Reference Manual (RM0383) and the Datasheet for W25Q64FV 64M-bit SPI Flash Memory .  Developing the SPI Driver Since some of the SPI1 and SPI3 peripheral pins are already occupied by the JTAG interface on the STM32F411 Discovery Board, we will use the SPI2 peripheral for our communication with the external flash memory. Remember to enable the clock to the GPIO Port B and SPI2 peripheral in the RCC registers. For driving the NSS line Low and High to Select and Deselect the Slave device, we can write functions...

What is AESecureIO? AESecureIO is an embedded system application developed on an STM32F401RET6 Nucleo-64 Development Board. It encrypts user-input data using AES-128 in Cipher Block Chain (CBC) Mode and stores it securely on an SD Card using the SDIO Interface. The application also supports the retrieval and decryption of data from the SD Card. This device utilizes the STM32F401 Microcontroller's SDIO (Secure Digital Input/Output) interface and the USART (Universal Synchronous/Asynchronous Receiver/Transmitter) peripheral. The SDIO interface manages data transfer between the microcontroller and the SD Card, while the USART peripheral enables data input and output through a serial monitor, such as PuTTY. The advantage of this device lies in the centralized approach to data encryption and decryption. By using a single point of encryption and decryption with a predefined 128-bit key , the device ensures that data retrieval can only be performed through it. This method grants the use...

Independent Watchdog The independent watchdog is based on a 12-bit downcounter and 8-bit prescaler. It is clocked from an independent 32 kHz internal RC and as it operates independently from the main clock, it can operate in Stop and Standby modes. It can be used either as a watchdog to reset the device when a problem occurs or as a free-running timer for application timeout management. It is hardware- or software-configurable through the option bytes(extracted from the Datasheet).  Read the presentation on the IWDG peripheral by STMicroelectronics. IWDG Registers The Independent Watchdog has few registers. They are IWDG Key Register (IWDG_KR) IWDG Prescaler Register (IWDG_PR) IWDG Reload Register (IWDG_RLR) IWDG Status Register (IWDG_SR) The Key register provides access protection to the Prescale Register and Reload Register. Writing 0x5555 to IWDG_KR enables write access to IWDG_PR and IWDG_RLR. Writing 0xAAAA loads the reload value stored in IWDG_RLR to the counte...

Direct Memory Access What is Direct Memory Access?  In embedded systems like the STM32F401 microcontroller, Direct Memory Access (DMA) is a feature that enhances the efficiency of data transfers between peripherals and memory without involving the CPU. DMA controllers are hardware blocks designed to offload data transfer tasks from the CPU, thereby reducing its workload and improving overall system performance. DMA operates by allowing peripherals such as ADCs, DACs, UARTs, and memory controllers to directly access the system's memory, either for reading data from memory or writing data to memory. This direct access eliminates the need for the CPU to intervene in each data transfer, making it particularly beneficial for high-speed data movement operations. If you want to read more about DMA, checkout this blog on embedded.com on Direct Memory Access . DMA Registers The DMA peripheral uses multiple registers for Interrupts, Configuration, and other peripheral-specific functionalitie...

Cyclic Redundancy Check Cyclic Redundancy Check, or CRC in short is an error-detecting code used to check data integrity in digital data. It involves executing the Modulo 2 Arithmetic division of a Message polynomial with a Generator polynomial and then appending the remainder of the division to the tail of the Message polynomial to get a complete Data frame for transmission. This is the process carried out on the Transmitter side. Then, on the Receiver side, another Modulo 2 Arithmetic Division is carried out with the same Generator polynomial to check for a 'zero' remainder, and if not found, an error has occurred. This is the basic layout of Cyclic Redundancy Check. If you want to get a better understanding of the process, check out Jacob Schrum's video on CRC  or Ben Eater's explanation on CRC working . If you are enthusiastic about diving deep into Checksums and CRC, check out the blogs maintained by Philip Koopman at Carnegie Mellon University . He has a lot to sh...

What is a Real-time Clock? Check out this article, Real-time clock from Wikipedia. It can get you started on what it is. In this tutorial, we will be talking about the integrated RTC peripheral on the STM32F401 microcontroller.  RTC Peripheral on the STM32F401RE The RTC is an independent Binary Coded Decimal counter. The RTC has two 32-bit registers that contain the         >  S econds,     > M inutes,      >  H ours (12- or 24-hour format),      >  D ay (Day of Week),      >  D ate (Day of Month),     >  M onth,      > Year, expressed in binary-coded decimal format (BCD). After the backup domain reset, all RTC registers are protected against possible parasitic write accesses. As long as the supply voltage remains in the operating range, the RTC never stops, regardless of the device status (Run mode, low-power mode, or under reset)....