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Independent Watchdog The independent watchdog is based on a 12-bit downcounter and 8-bit prescaler. It is clocked from an independent 32 kHz internal RC and as it operates independently from the main clock, it can operate in Stop and Standby modes. It can be used either as a watchdog to reset the device when a problem occurs or as a free-running timer for application timeout management. It is hardware- or software-configurable through the option bytes(extracted from the Datasheet).  Read the presentation on the IWDG peripheral by STMicroelectronics. IWDG Registers The Independent Watchdog has few registers. They are IWDG Key Register (IWDG_KR) IWDG Prescaler Register (IWDG_PR) IWDG Reload Register (IWDG_RLR) IWDG Status Register (IWDG_SR) The Key register provides access protection to the Prescale Register and Reload Register. Writing 0x5555 to IWDG_KR enables write access to IWDG_PR and IWDG_RLR. Writing 0xAAAA loads the reload value stored in IWDG_RLR to the counter. Writing 0xCCCC e

Direct Memory Access What is Direct Memory Access?  In embedded systems like the STM32F401 microcontroller, Direct Memory Access (DMA) is a feature that enhances the efficiency of data transfers between peripherals and memory without involving the CPU. DMA controllers are hardware blocks designed to offload data transfer tasks from the CPU, thereby reducing its workload and improving overall system performance. DMA operates by allowing peripherals such as ADCs, DACs, UARTs, and memory controllers to directly access the system's memory, either for reading data from memory or writing data to memory. This direct access eliminates the need for the CPU to intervene in each data transfer, making it particularly beneficial for high-speed data movement operations. If you want to read more about DMA, checkout this blog on embedded.com on Direct Memory Access . DMA Registers The DMA peripheral uses multiple registers for Interrupts, Configuration, and other peripheral-specific functionalitie

Cyclic Redundancy Check Cyclic Redundancy Check, or CRC in short is an error-detecting code used to check data integrity in digital data. It involves executing the Modulo 2 Arithmetic division of a Message polynomial with a Generator polynomial and then appending the remainder of the division to the tail of the Message polynomial to get a complete Data frame for transmission. This is the process carried out on the Transmitter side. Then, on the Receiver side, another Modulo 2 Arithmetic Division is carried out with the same Generator polynomial to check for a 'zero' remainder, and if not found, an error has occurred. This is the basic layout of Cyclic Redundancy Check. If you want to get a better understanding of the process, check out Jacob Schrum's video on CRC  or Ben Eater's explanation on CRC working . If you are enthusiastic about diving deep into Checksums and CRC, check out the blogs maintained by Philip Koopman at Carnegie Mellon University . He has a lot to sh