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Building a Software RNG v1.0 with Timers, LFSR, XOR Shift, and FNV Hash algorithms

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Why a Software Random Number Generator? The STM32F401 microcontroller lacks a hardware Random Number Generator (RNG), making a Software RNG necessary for generating random numbers. While hardware RNGs provide higher-quality randomness, a Software RNG can still achieve essential functionality by generating unique cryptographic keys, mimicking real-world randomness, and introducing system unpredictability. How the Software RNG Generates Random Numbers The execution of the Software RNG begins by Generating a Hardware seed using the STM32 timers , providing a source of entropy based on system behavior. Then, a Linear Feedback Shift Register (LFSR) is applied to the seed to add a bit of randomness by shifting and modifying the seed value. The result of the LFSR operation is then combined with the hardware seed using the XOR (Exclusive OR) operation . Finally, the combined result is processed using the FNV Hash function, which generates a 32-bit random number. Extracting Hardware-based See
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Audio Processing Series Part IV : Encoding and Decoding audio data using ADPCM algorithm

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Understanding ADPCM: Principles & Implementation ADPCM (Adaptive Differential Pulse Code Modulation) is an audio compression technique that focuses on encoding the difference between consecutive audio samples instead of their absolute values. By representing only the changes in audio data, ADPCM achieves significant data rate reductions. This project involves reading an audio file in blocks of 1024 samples, encoding it using ADPCM, and storing the ADPCM code in flash memory. Afterward, the ADPCM code will be retrieved from the flash memory, decoded, and the decompressed audio saved back to flash. Both the ADPCM code and the decompressed audio data will be written to the flash memory for analysis of audio quality. The flash memory has a capacity of 8 megabytes, and since the original uncompressed audio file is approximately 938 kilobytes, space will be allocated as follows: the original audio will be stored at the beginning of the flash memory, the ADPCM code will start at page 8192
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Audio Processing Series Part II : Storing Audio data on external Serial Flash Memory

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Storing Audio data in an SPI Flash Memory This is the second article of the Audio Processing Project on the STM32 F411 Discovery Board. This article focuses on developing the SPI driver and the Library for the W25Q64FV 64 M-bit Serial Flash Memory from Winbond. The W25Qxx series of chips are Serial NOR Flash memory devices with capacities ranging from 4 MB to 128 MB and utilize the Serial Peripheral Interface for communication with microcontrollers. Checkout the STM32F411 Reference Manual (RM0383) and the Datasheet for W25Q64FV 64M-bit SPI Flash Memory .  Developing the SPI Driver Since some of the SPI1 and SPI3 peripheral pins are already occupied by the JTAG interface on the STM32F411 Discovery Board, we will use the SPI2 peripheral for our communication with the external flash memory. Remember to enable the clock to the GPIO Port B and SPI2 peripheral in the RCC registers. For driving the NSS line Low and High to Select and Deselect the Slave device, we can write functions that set
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Audio Processing Series Part III : Designing an Echo effect

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Echo Algorithm & Parameter Tuning The echo effect is a widely used audio processing technique that mimics sound reflections in different environments. Fundamentally, the echo algorithm works by capturing an audio input, introducing a delay to the signal, and blending it back with the original sound. This method requires fine-tuning parameters like delay time, feedback, and amplitude, enabling the generation of multiple repetitions that can differ in intensity and timing. Delay time specifies how long it takes for the echoed sound to return, while feedback determines the amount of the output signal that is redirected back into the input. The delay time is set to 300 milliseconds, determining the duration between the original signal and its echoed repetition. This value creates a noticeable gap that allows listeners to perceive the echo distinctly. The feedback level is configured to 0.7, which indicates that 70% of the output signal is fed back into the input.  Reading Audio Data fr
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Designing a Software-Based Wear Leveling Subsystem for W25Q64FV Serial Flash Memory

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NOR Flash Memories & the Need for Wear Leveling NOR Flash is a type of non-volatile memory used to store data that needs to persist even when a device is powered off. NOR Flash is typically organized into sectors or blocks, which can be individually erased and reprogrammed.  Due to the physics of flash cell structure, memory cells suffer from “wear” with every Program/Erase cycle (P/E cycle). This means flash memory has a finite usable life. If a flash memory exceeds this limit, the storage capability becomes unreliable. Wear Leveling is a common technique used by storage media  to enhance the longevity of the storage media. Flash memory cells can only be programmed from a 1 to a 0 state. In order to set any cell from 0 to 1 state, the cell has to be erased to a 1. In order to update any already programmed memory sectors/blocks, the sectors/blocks have to be first erased and then reprogrammed, hence the P/E cycle. Depending on how often an application updates the flash content, fre
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